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Datasheet, Confidential - D e t a i l e d D e s c r i p t i o n I C m o d e S e r i a l D a t a B u s
The AS3665 supports the I C bus protocol. A device that sends data onto the bus is defined as a transmitter and a
the I C bus. Within the bus specifications a standard mode (100kHz maximum clock rate) and a fast mode (400kHz
Table 53. I C Address Selection
AS3665
2
I 2 C mode Serial Data Bus
2
device receiving data as a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the
bus access, and generates the START and STOP conditions must control the bus. The AS3665 operates as a slave on
2
maximum clock rate) are defined. The AS3665 works in both modes. Connections to the bus are made through the
open-drain I/O lines SDA and SCL.
I 2 C Address selection
The slave address can be selected depending on the external resistor R ADDR connected to the pin ADDR. The actual
address for reading and writing is selected according to Table 53 .
2
I C Address for
R ADDR
> 320k Ω (leave R ADDR open)
320k Ω
160k Ω
80k Ω
40k Ω
20k Ω
10k Ω
0k Ω (short to GND)
Writing
80h
82h
84h
86h
88h
8Ah
8Ch
8Eh
2 1
Reading
81h
83h
85h
87h
89h
8Bh
8Dh
8Fh
1. This I C address has 8 bits and includes the R/W flag (LSB). If a 7 bits address is required, use the 7 MSBs.
2
The following bus protocol has been defined ( Figure 21 ):
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy
Both data and clock lines remain HIGH.
Start Data Transfer
A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.
Stop Data Transfer
A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.
Data Valid
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of
the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal.
There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes
transferred between START and STOP conditions are not limited, and are determined by the master device. The
information is transferred byte-wise and each receiver acknowledges with a ninth bit.
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